1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to damascene interconnects exhibiting reduced short circuit formation and a method for fabricating these interconnects.
2. Description of the Relevant Art
Fabrication of an integrated circuit involves numerous processing steps. To form a metal-oxide-semiconductor (MOS) integrated circuit, for example, a gate dielectric, typically formed from silicon dioxide ("oxide"), is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and drain. Such transistors are connected to each other and to terminals of the completed integrated circuit using conductive interconnect lines. Typically, multiple levels of interconnect are needed to provide the connections necessary for a modern, high-transistor-density IC.
A pervasive trend in modem integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modem day processes employ features, such as gate conductors and interconnects, which have less than 0.3 .mu.m critical dimension. As feature size decreases, the sizes of the resulting transistors as well as those of the interconnects between transistors also decrease. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
This trend toward reduced feature sizes imposes severe demands on many aspects of IC fabrication, including interconnect formation. For example, narrower interconnects have reduced cross-sectional area, which results in a higher interconnect resistance for a given interconnect material. This interconnect resistance, along with the capacitance of the interconnect with respect to ground and other interconnects, contributes to an RC time constant which characterizes delays associated with propagation along the interconnect line. Fabrication of a circuit with increased RC time constants lowers the speed at which the circuit can operate by increasing the time needed, for example, for a circuit output voltage to respond to a change in input voltage. Although there are other parasitic resistances and capacitances in an integrated circuit, such as those associated with the transistors themselves, in modem circuits having submicron feature sizes interconnects may contribute as much as 80% of the total circuit delay time. The increased interconnect resistance described above places a limit on how narrow interconnect lines can be and maintain tolerable interconnect resistance. The greater the resistivity of the interconnect material, the wider the lines must be, as discussed further below.
As feature size decreases and transistor density increases, multiple layers of interconnect must be used to connect the transistors to each other and to the terminals of the integrated circuit. The limitation discussed above on the narrowness of interconnect lines can exacerbate this need for multiple interconnect layers. Fabrication of each interconnect layer requires deposition and patterning processes, adding to the expense of the circuit and increasing the opportunity for defect incorporation and the resulting yield reduction. It is therefore desirable to minimize the number of interconnect layers required.
Lowering the resistivity of the interconnect material alleviates the interconnect-related problems discussed above. Resistance, R, along the length of a structure formed from a given material is related to the resistivity, .rho., of the material by R=.rho.l/A, where l is the length of the structure and A is its cross-sectional area. It can therefore be seen that lowering the resistivity of an interconnect material reduces the resistance of an interconnect line of a given cross-sectional area. Furthermore, a line formed from a lower-resistivity material could be made narrower before an unacceptable resistance level is reached than a line formed from a higher-resistivity material. This ability to form narrower lines may allow fewer interconnect levels to be used to form the required connections for an IC, thereby reducing costs and potentially increasing the yield of correctly-functioning circuits.
Advantages such as those described above of low-resistivity interconnect materials have driven a movement in the semiconductor industry toward replacing aluminum interconnects with interconnects made from copper. The resistivity of pure copper (about 1.7 .mu..OMEGA..multidot.cm) is significantly lower than that of pure aluminum (about 2.6 .mu..OMEGA..multidot.cm). Both aluminum and copper interconnects typically contain small concentrations of other elements to improve interconnect reliability. These added elements increase the resistivity of the metal, but practical copper interconnects still have resistivities up to 40% lower than those of practical aluminum interconnects. Copper interconnects can therefore be made narrower than aluminum interconnects for a given value of interconnect resistance. This may result in fewer levels of metallization being needed with copper interconnects. For a given interconnect cross-sectional area, copper interconnects exhibit lower resistances, and therefore shorter interconnect-related delays, than do aluminum interconnects.
Because copper is more difficult to etch than aluminum, in addition to difficulties in etching narrow features in metals in general as compared to etching of insulators, copper interconnects are generally formed using what is known as a damascene process. Instead of blanket-depositing a metal, which is then patterned into interconnect lines or vias (vertical connections between interconnect levels), and subsequently filling in the spaces between the lines or vias with an insulator for electrical isolation, interconnect formation using a damascene process involves patterning trenches corresponding to the desired interconnect geometry into a dielectric, and then filling the trenches with the interconnect metal.
A typical copper damascene process is illustrated in FIGS. 1-4. In the cross-sectional view of FIG. 1, via dielectric 12 is formed upon semiconductor topography 10. Semiconductor topography 10 includes a semiconductor substrate, preferably a silicon substrate, and may include transistors formed on and within the substrate, and one or more layers of interconnect. Via dielectric 12, typically formed from oxide, provides electrical isolation between semiconductor topography 10 and a layer of interconnect to be formed above via dielectric 12. Connections between topography 10 and this overlying interconnect layer are made by opening via trenches through via dielectric 12. Etch stop layer 14 and line dielectric 16 are formed above via dielectric 12.
The process of FIGS. 1-4 is specifically known as a "dual damascene" process, in which the same metal is used for vias and overlying interconnect lines, and both via and line dielectrics are deposited before trench formation and filling. In a single damascene process, on the other hand, vias are formed before deposition of a line dielectric and subsequent trench formation and filling to create interconnect lines. Vias and lines may be formed from different dielectrics in single damascene processes. Etch stop layer 14 is formed from a dielectric material which exhibits etch selectivity with respect to via dielectric 12 and line dielectric 16. For example, silicon nitride is often used for etch stop 14. Line dielectric 16 is often formed using a low-permittivity material, such as fluorine-doped oxide. The use of a low-permittivity material reduces capacitive coupling between closely spaced interconnect lines. Dielectrics 12 and 16 and etch stop 14 are typically deposited using chemical vapor deposition (CVD) techniques.
Patterning and etching are subsequently carried out to form trenches in line dielectric 16 and via dielectric 12. An example of the resulting trenches is shown in FIG. 2. Trench 18 includes a via trench extending through via dielectric 12 down to the upper surface of semiconductor 10, and an overlying interconnect line trench connected to topography 10 by this via trench. Trench 20 is for an interconnect line which does not have a via connection to topography 10 in the plane of the cross-section of FIG. 2. Trenches 18 and 20 are preferably formed using photolithographic patterning processes and anisotropic dry etching processes. There are several variations of patterning/etching sequences which may be used to form trenches 18 and 20. For example, line trenches such as trench 20 and the upper part of trench 18 may be patterned and etched first, followed by patterning and etching of via trenches, such as the lower part of trench 18. Alternatively, via trenches may be patterned and etched before line trenches, or, with appropriate patterning, both line and via trenches may be etched in one step. Although etch stop layers such as layer 14 are often used in dual damascene processes, it may be possible to form trenches such as trench 18 without using an etch stop layer. Furthermore, via dielectric 12 and line dielectric 16 may be formed from the same material in some dual damascene processes.
Copper (or another interconnect metal) is subsequently deposited to fill trenches 18 and 20, as shown in FIG. 3. Because copper diffuses readily through silicon and oxide, and undesirably alters the electrical properties of transistors formed in silicon, liner 22 is deposited into the trenches before deposition of copper layer 24. Liner 22 is preferably formed from a conductive material which acts as a diffusion barrier to the overlying copper, and also adheres well to dielectrics 12 and 16. Materials typically used for liner 22, which is often called a diffusion barrier and/or an adhesion layer, include metal nitrides such as titanium nitride and tantalum nitride, and refractory alloys such as titanium-tungsten. Copper layer 24 is typically formed using two deposition steps. A thin "seed" layer is deposited first, followed by a more rapid "fill" deposition. The seed layer is typically deposited by sputtering, but other methods such as CVD may also be used. Electroplating is a currently preferred method of depositing the copper fill layer, but other techniques, including CVD, may be used as well.
Portions of liner 14 and copper layer 24 external to trenches 18 and 20 are subsequently removed, as shown in FIG. 4. This removal is preferably accomplished using chemical-mechanical polishing (CMP), in which the upper surface of the wafer is polished using an abrasive polishing pad and a polishing fluid known as a slurry. Copper interconnects 26 (a line/via combination) and 28 (a line interconnect), shown in FIG. 4, result from this removal. Liner portions 27 and 29 underlie interconnects 26 and 28, respectively. The interconnect level containing interconnects 26 and 28 is typically covered by cap layer 30, which has a composition similar to that of etch stop layer 14. Cap layer 30 is an insulating film which provides a diffusion barrier to prevent copper from diffusing into an overlying dielectric.
A problem which can arise with damascene interconnect structures such as that of FIG. 4 is shown in FIG. 5. FIG. 5 is an expanded view of the area between interconnects 26 and 28 in FIG. 4. Copper "tails" 32 extend outward from interconnects 26 and 28, along the interface between line dielectric 16 and cap layer 30. Tails 32 result from "extrusion", a movement of copper atoms along the interface in response to an electric field applied between interconnects 26 and 28. Because connection points of an integrated circuit are at a variety of electrostatic potentials, potential differences, and associated electric fields, may often exist between adjacent interconnect lines. It is postulated that the interface between dielectric 16 and cap layer 30 provides a ready diffusion path for copper atoms, and that this diffusion may be aided by an electric field. Thermal expansions and contractions caused by subsequent processing and by heating of conductors during circuit operation may also contribute to extrusion of tails 32.
Extrusion is believed to be somewhat analogous to the electromigration which can occur in current-carrying metal lines, in which metal atoms move by diffusion along grain boundaries, the motion of the atoms being aided by collisions with the electrons constituting the current. As such, metals which tend to be susceptible to electromigration are believed to also be susceptible to extrusion, when used in structures which provide an interfacial diffusion path, such as damascene interconnect structures (including single or dual damascene). Lower-melting point metals such as aluminum and copper tend to be susceptible to electromigration, and are therefore believed to be susceptible to extrusion in damascene interconnect structures. Such extrusion can cause short circuits between interconnect lines, leading to circuit failure.
It would therefore be desirable to develop a damascene process and structure which minimizes extrusion of interconnect metals. In particular, a copper damascene process in which extrusion is minimized while the resistivity benefits of copper are maintained would be desirable.